There are two main types of high-speed serial interface clocking solutions: source-synchronous and embedded clock. For embedded clock solutions the data stream must include sufficient clock information in order to synchronize the receiver in a reliable way. Embedded clock solutions can run at higher rates because there is no data-clock transmission-path matching issue. However, the embedded clock receiver needs clock and data recovery (CDR), compared to the straightforward data slicing with the provided clock in the source-synchronous case.
Embedded clock type solutions can be subdivided in a few categories:
1. A synchronous full-rate or half rate bit clock or any other lower frequency clock with a fixed and known ratio (e.g. byte or word clock) is transmitted from TX to RX, but it is not kept phase-synchronized with the data. TX and RX share the same clock frequency (or a known and fixed ratio), and the receiver only needs to do phase alignment (and clock multiplication in case a lower frequency fixed-ratio clock is transmitted).
2. The receiver does not get a reference clock signal from the transmit side, but the receiver locks to the embedded clock in the data stream and recovers that way both clock and data information from it. This is possible if the data stream is properly encoded to include sufficient clock information. For binary transmission this can for instance be achieved with 8B10B codes. In order to avoid false locking on (sub)harmonics there must be either some locking aid provided or the data encoding must implicitly provide sufficient frequency information (eg. bi-phase, Manchester code). For coding efficiency reasons using locking aids are preferred in many cases. Locking aids can for instance be a local receiver reference clock, which helps to become close to the data rate, and/or a training sequence in the data stream.
3. The receiver does not get a reference clock signal from the transmit side, but transmitter and receiver each have a local reference clock, which frequencies are known to be close together (ppm's difference), but not exactly equal (plesiochronous clocks). The receiver clocks remain locked to the local reference and data is recovered in the digital domain by over-sampling the data stream.
If the receiver clock signal locks on the local reference before data is transmitted, and then synchronizes to the data stream with a training sequence before actual payload data transmission, the local reference clock functions as locking aid and this is covered under option 2.
Type 2 and 3 require fewer connections then type 1 (or source synchronous solutions), as they do not need a separate clock signal to be transmitted. However, for type 2 the synchronization becomes more complicated because, besides phase synchronization, the receiver must first lock to the right frequency before reliable data reception becomes possible. Type 3 solutions can start-up rather fast using the knowledge that the reference frequencies are very close and provided that the clock signals are operational. However, this type 3 conventionally requires availability of nearly equal reference frequencies at both ends, which might not be trivial and may require additional reference (probably crystal) oscillators in the system. Type 1 is less attractive because it implies more connections and costs more 10 power then types 2 and 3.